n-channel jfet switch 2n5432 C 2n5434 features low r ds(on) excellent switching low cutoff current absolute maximum ratings (t a = 25 o c unless otherwise noted) gate-source voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25v gate-drain voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25v gate current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100ma drain current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ma storage temperature range . . . . . . . . . . . . . -65 o c to +200 o c operating temperature range . . . . . . . . . . . -55 o c to +150 o c lead temperature (soldering, 10sec) . . . . . . . . . . . . . +300 o c power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300mw derate above 25 o c . . . . . . . . . . . . . . . . . . . . . . . 2.3mw/ o c note: stresses above those listed under "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only and func tional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. ordering information part package temperature range 2n5432-34 hermetic to-52 -55 o c to +150 o c x2n5432-34 sorted chips in carriers -55 o c to +150 o c llc pin configuration d s (to-52) g, c electrical characteristics (t a = 25 o c unless otherwise specified) symbol parameter 2n5432 2n5433 2n5434 units test conditions min max min max min max i gss gate reverse current -200 -200 -200 pa v gs = -15v, v ds = 0 -200 -200 -200 na t a = 150 o c bv gss gate-source breakdown voltage -25 -25 -25 v i g = -1 m a, v ds = 0 i d(off) drain cutoff current 200 200 200 pa v ds = 5v, v gs = -10v 200 200 200 na t a = 150 o c v gs(off) gate-source cutoff voltage -4 -10 -3 -9 -1 -4 v v ds = 5v, i d = 3na i dss saturation drain current (note 1) 150 100 30 ma v ds = 15v, v gs = 0 r ds(on) static drain-source on resistance 2 5 7 10 ohm v gs = 0, i d = 10ma v ds(on) drain-source on voltage 50 70 100 mv r ds(on) drain-source on resistance 5 7 10 ohm v gs = 0, i d = 0 f = 1khz c iss common-source input capacitance (note2) 30 30 30 pf v ds = 0, v gs = -10 v f = 1mhz c rss common-source reverse transfer capacitance (note 2) 15 15 15 t d turn-on delay time (note 2) 4 4 4 ns v dd = 1.5v, v gs (on) = 0, v gs(off) = -12v, i d(on) = 10ma t r rise time (note 2) 1 1 1 t off turn-off delay time (note 2) 6 6 6 t f fall time (note 2) 30 30 30 notes: 1. pulse test required, pulsewidth 300 m s, duty cycle 3%. 2. for design reference only, not 100% tested. 5018
2n5432 C 2n5434 llc switching time, test circuit d s = r l v in 50 w r g v out v dd 0090 d(on) i v ds(on) - v dd sampling scope input pulse rise time 0.4ns input resistance 10m w input capacitance 1.5pf fall time 0.75ns pulse width 200ns pulse rate 550pps rise time 0.25ns
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